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integrated silicon solution, inc. www.issi.com 1 rev.? d ? 08/11/2011 is61nlf12836a/is61nvf12836a is61nlf25618a/is61nvf25618a? ? copyright ? 2011 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this specifcation and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtain the latest version of this device specifcation before relying on any published information and before placing orders for products. integrated silicon solution, inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to signifcantly affect its safety or effectiveness. products are not authorized for use in such applications unless integrated silicon solution, inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of integrated silicon solution, inc is adequately protected under the circumstances features ? 100 percent bus utilization ? no wait cycles between read and write ? internal self-timed write cycle ? individual byte write control ? single read/write control pin ? clock controlled, registered address, data and control ? interleaved or linear burst sequence control us- ing mode input ? three chip enables for simple depth expansion and address pipelining ? power down mode ? common data inputs and data outputs ? cke pin to enable clock and suspend operation ? jedec 100-pin tqfp, 119-ball pbga, and 165- ball pbga packages ? power supply: nvf: v dd 2.5v ( 5%), v ddq 2.5v ( 5%) nlf: v dd 3.3v ( 5%), v ddq 3.3v/2.5v ( 5%) ? industrial temperature available ? lead-free available description the 4 meg 'nlf/nvf' product family feature high-speed, low-power synchronous static rams designed to provide a burstable, high-performance, 'no wait' state, device for networking and communications applications. they are organized as 128k words by 36 bits and 256k words by 18 bits, fabricated with issi 's advanced cmos technology. incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to write, or write to read. this device integrates a 2-bit burst counter, high-speed sram core, and high-drive capability outputs into a single monolithic circuit. all synchronous inputs pass through registers are controlled by a positive-edge-triggered single clock input. operations may be suspended and all synchronous inputs ignored when clock enable, cke is high. in this state the internal device will hold their previous values. all read, write and deselect cycles are initiated by the adv input. when the adv is high the internal burst counter is incremented. new external addresses can be loaded when adv is low. write cycles are internally self-timed and are initiated by the rising edge of the clock inputs and when we is low. separate byte enables allow individual bytes to be written. a burst mode pin (mode) defnes the order of the burst sequence. when tied high, the interleaved burst sequence is selected. when tied low, the linear burst sequence is selected. 128k?x?36?and?256k?x?18 4mb, ? flow? through ?'no? wait' ? state ? bus?sram august ?2011 fast ? access? time symbol? parameter ? 6.5? 7.5? units t kq clock access time 6.5 7.5 ns t kc cycle time 7.5 8.5 ns frequency 133 117 mhz
2 integrated silicon solution, inc. www.issi.com rev.? d 08/11/2011 ? is61nlf12836a/is61nvf12836a is61nlf25618a/is61nvf25618a? ? block? diagram ad v we } bw ? x (x= a-d, or a,b) ce ce2 ce2 contr ol logic 128kx36; 256kx18 memor y arra y write address register write address register contr ol logic buffer address register x 36: a [0:16] or x 18: a [0:17] clk cke a2-a16 or a2-a17 a0-a1 a'0-a'1 burs t address counter mode da t a-in register da t a-in register contr ol register oe zz 36 or 18 k k dqx/dqpx k k
integrated silicon solution, inc. www.issi.com 3 rev.? d ? 08/11/2011 ? is61nlf12836a/is61nvf12836a is61nlf25618a/is61nvf25618a? ? bottom view 165-ball, 13 mm x 15mm bga bottom view 119-ball, 14 mm x 22 mm bga
4 integrated silicon solution, inc. www.issi.com rev.? d 08/11/2011 ? is61nlf12836a/is61nvf12836a is61nlf25618a/is61nvf25618a? ? 1 2 3 4 5 6 7 8 9 10 11 a nc a ce bwc bwb ce2 cke adv nc a nc b nc a ce2 bwd bwa clk we oe nc a nc c dqpc nc v ddq v ss v ss v ss v ss v ss v ddq nc dqpb d dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb e dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb f dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb g dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb h nc nc nc v dd v ss v ss v ss v dd nc nc zz j dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa k dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa l dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa m dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa n dqpd nc v ddq v ss nc nc nc v ss v ddq nc dqpa p nc nc a a nc a1* nc a a a nc r mode nc a a nc a0* nc a a a a note: a0 and a1 are the two least signifcant bits (lsb) of the address feld and set the internal burst counter if burst is desired. pin?descriptions s ymbol pin name a address inputs a0, a1 synchronous burst address inputs adv synchronous burst address advance/ load we synchronous read/write control input clk synchronous clock cke clock enable ce, ce2, ce2 synchronous chip enable bwx (x=a-d) synchronous byte write inputs oe output enable zz power sleep mode mode burst sequence selection v dd 3.3v/2.5v power supply nc no connect dqx data inputs/outputs dqpx parity data i/o v ddq isolated output power supply 3.3v/2.5v v ss g round pin?c onfiguration?? ?128k? x ? 36, ?165-ball?pbga?(t op? view)?
integrated silicon solution, inc. www.issi.com 5 rev.? d ? 08/11/2011 ? is61nlf12836a/is61nvf12836a is61nlf25618a/is61nvf25618a? ? 119-pin?pbga? package? configuration???????128k?x?36? (top? view)? 1 2 3 4 5 6 7 a a bwb b nc c nc d dqc dqpc vss e dqc dqc vss f v ddq dqc g dqc dqc h dqc dqc j v ddq v dd k dqd dqd l dqd dqd m v ddq dqd n dqd dqd vss p nc dqpd r a ce2 mode a 0 * a a a v ss v ss v ss v ss bwd v ss v ss v ss nc nc v dd v dd v dd v dd nc vss vss vss vss vss nc ce2 nc a nc t u v ddq nc v ddq dqd a nc nc nc a a bwc nc a 1 * cke nc clk nc we nc oe ce nc adv nc a nc bwa a a a dqpa dqa dqa dqa dqa dqb dqb dqb dqb dqpb a a v ddq zz dqa dqa v ddq dqa dqa v ddq dqb dqb v ddq dqb dqb nc v ddq v ss note: a0 and a1 are the two least signifcant bits (lsb) of the address feld and set the internal burst counter if burst is desired. pin?descriptions symbol pin name a address inputs a0, a1 synchronous burst address inputs adv synchronous burst address advance/ load 80 synchronous read/write control input clk synchronous clock 10 clock enable 0 synchronous chip select 0 2 synchronous chip select ce2 synchronous chip select /8x (x=a-d) synchronous byte write inputs 20 output enable zz power sleep mode mode burst sequence selection v 1 1 power supply v cc ground nc no connect dqa-dqd data inputs/outputs dqpa-pd parity data i/o v 0 output power supply
6 integrated silicon solution, inc. www.issi.com rev.? d 08/11/2011 ? is61nlf12836a/is61nvf12836a is61nlf25618a/is61nvf25618a? ? 165-pin?pbga? package? configuration???????256k?x?18? (top? view)? pin?descriptions symbol pin name a address inputs a0, a1 synchronous burst address inputs adv synchronous burst address advance/ load we synchronous read/write control input clk synchronous clock cke clock enable ce, ce2, ce2 synchronous chip enable bwx (x=a,b) synchronous byte write inputs oe output enable zz power sleep mode 1 2 3 4 5 6 7 8 9 10 11 a a bwb cke b n c a we oe c n c nc vss vss d n c dqb vss vss nc e n c dqb vss vss vss f nc dqb nc g n c dqb nc nc h n c nc v ddq j dqb nc dqa k dqb nc l dqb nc vss m dqb nc vss n dqpb nc vss vss nc p n c nc a 1 * nc r mode a nc ce2 vss vss vss vss vss vss vss vss nc nc a a a a a a a a a a a nc nc a a ce v ddq v dd q v ddq v dd q v ddq v ddq v dd q v ddq v ddq v ddq nc nc v dd v dd v dd v dd v dd v dd v dd v dd v dd nc bwa vss vss vss vss vss vss vss vss nc nc nc ce2 clk vss nc a 0 * nc vss vss vss vss vss vss adv v dd v dd v dd v dd v dd v dd v dd v dd v dd v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq nc nc nc dqa dqa dqa nc nc nc nc nc nc nc zz dqa dqa dqa dqa dqpa note: a0 and a1 are the two least signifcant bits (lsb) of the address feld and set the internal burst counter if burst is desired. mode burst sequence selection v dd 3.3v/2.5v power supply nc no connect dqx data inputs/outputs dqpx parity data i/o v ddq isolated output power supply 3.3v/2.5v v cc 1 o round
integrated silicon solution, inc. www.issi.com 7 rev.? d ? 08/11/2011 ? is61nlf12836a/is61nvf12836a is61nlf25618a/is61nvf25618a? ? 119-pin?pbga? package? configuration???????256k?x?18? (top? view)? pin?descriptions symbol pin name a address inputs a0, a1 synchronous burst address inputs adv synchronous burst address advance/ load we synchronous read/write control input clk synchronous clock cke clock enable ce synchronous chip select ce 2 synchronous chip select ce2 synchronous chip select bwx (x=a,b) synchronous byte write inputs oe output enable zz power sleep mode mode burst sequence selection v dd power supply v ss ground nc no connect dqa-dqb data inputs/outputs dqpa-pb parity data i/o v ddq output power supply 1 2 3 4 5 6 7 a a b nc c nc d dqb vss e dqb vss f v ddq g dqb h dqb j v ddq v dd k dqb l dqb m v ddq dqb n dqb nc vss p nc dqpb r a ce2 mode a a 0 * a a v ss v ss v ss v ss nc v ss v ss nc nc v dd v dd v dd v dd nc vss vss vss vss vss nc ce2 nc a nc t u v ddq nc v ddq a nc nc nc a a bwb nc a 1 * cke nc clk nc we nc oe ce nc adv nc a nc bwa a a a dqpa dqa dqa dqa dqa a a v ddq zz dqa dqa v ddq dqa dqa v ddq v ddq nc v ddq nc nc nc nc nc nc nc nc a v ss v ss nc nc nc nc nc nc nc nc nc note: a0 and a1 are the two least signifcant bits (lsb) of the address feld and set the internal burst counter if burst is desired.
8 integrated silicon solution, inc. www.issi.com rev.? d 08/11/2011 ? is61nlf12836a/is61nvf12836a is61nlf25618a/is61nvf25618a? ? pin? configuration 100-pin? tqfp 256k?x?18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 a nc nc v ddq vss nc dqp a dqa dqa vss v ddq dqa dqa vss nc v dd zz dqa dqa v ddq vss dqa dqa nc nc vss v ddq nc nc nc nc nc nc v ddq vss nc nc dqb dqb vss v ddq dqb dqb nc v dd nc vss dqb dqb v ddq vss dqb dqb dqpb nc vss v ddq nc nc nc a a ce ce2 nc nc bw b bw a ce2 v dd vss clk we cke oe adv nc nc a a mode a a a a a1 a0 nc nc vss v dd nc nc a a a a a a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 dqpb dqb dqb v ddq vss dqb dqb dqb dqb vss v ddq dqb dqb vss nc v dd zz dqa dqa v ddq vss dqa dqa dqa dqa vss v ddq dqa dqa dqp a dqpc dqc dqc v ddq vss dqc dqc dqc dqc vss v ddq dqc dqc nc v dd nc vss dqd dqd v ddq vss dqd dqd dqd dqd vss v ddq dqd dqd dqpd a a ce ce2 bw d bwc bw b bw a ce2 v dd vss clk we cke oe ad v nc nc a a mode a a a a a1 a0 nc nc vss v dd nc nc a a a a a a a 128k?x?36 pin?descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a synchronous address inputs clk synchronous clock adv synchronous burst address advance /8a-/8 d synchronous byte write enable 80 write enable 10 clock enable vss ground for core nc not connected 0, ce2, 0c synchronous chip enable 20 output enable dqa-dqd synchronous data input/output dqpa-dqpd parity data i/o mode burst sequence selection v +3.3v/2.5v power supply v cc ground for output buffer v 0 isolated output buffer supply: +3.3v/2.5v zz snooze enable
integrated silicon solution, inc. www.issi.com 9 rev.? d ? 08/11/2011 ? is61nlf12836a/is61nvf12836a is61nlf25618a/is61nvf25618a? ? synchronous ? truth ? table (1) ? address ? operation? used? ce? ce2 ce2 adv we ? bwx? oe? cke clk not selected n/a h x x l x x x l not selected n/a x l x l x x x l not selected n/a x x h l x x x l not selected continue n/a x x x h x x x l begin burst read external address l h l l h x l l continue burst read next address x x x h x x l l nop/dummy read external address l h l l h x h l dummy read next address x x x h x x h l begin burst write external address l h l l l l x l continue burst write next address x x x h x l x l nop/write abort n/a l h l l l h x l write abort next address x x x h x h x l ignore clock current address x x x x x x x h notes: 1. "x" means don't care. 2. the rising edge of clock is symbolized by 3. a continue deselect cycle can only be entered if a deselect cycle is executed frst. 4. we = l means write operation in write truth table. we = h means read operation in write truth table. 5. operation fnally depends on status of asynchronous pins (zz and oe). burst read deselect burs t write begin read begin write read write read write burs t burst burs t ds ds ds read ds ds read write write burst burs t write read state ? diagram
10 integrated silicon solution, inc. www.issi.com rev.? d 08/11/2011 ? is61nlf12836a/is61nvf12836a is61nlf25618a/is61nvf25618a? ? asynchronous ? truth ? table (1) operation? zz? oe? i/o? status sleep mode h x high-z read l l dq l h high-z write l x din, high-z deselected l x high-z notes: 1. x means "don't care". 2. for write cycles following read cycles, the output buffers must be disabled with oe, otherwise data bus contention will occur. 3. sleep mode means power sleep mode where stand-by current does not depend on cycle time. 4. deselected means power sleep mode where stand-by current depends on cycle time. write? truth ? table ? (x18) operation? we bwa bwb read h x x write byte a l l h write byte b l h l write all bytes l l l write abort/nop l h h notes: 1. x means "don't care". 2. all inputs in this table must beet setup and hold time around the rising edge of clk.
integrated silicon solution, inc. www.issi.com 11 rev.? d ? 08/11/2011 ? is61nlf12836a/is61nvf12836a is61nlf25618a/is61nvf25618a? ? interleaved ? burst?address? table ? (mode = v dd or nc) ? external? address? 1st? burst? address? 2nd? burst? address? 3rd ? burst? address? ? a1? a0 ? a1? a0 ? a1? a0 ? a1? a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 write? truth ? table ? (x36) operation? we bw a bwb bwc bwd read h x x x x write byte a l l h h h write byte b l h l h h write byte c l h h l h write byte d l h h h l write all bytes l l l l l write abort/nop l h h h h notes : 1. x means "don't care". 2. all inputs in this table must beet setup and hold time around the rising edge of clk.
12 integrated silicon solution, inc. www.issi.com rev.? d 08/11/2011 ? is61nlf12836a/is61nvf12836a is61nlf25618a/is61nvf25618a? ? operating ?range?(is61nlfx) ? range ? ambient? temperature ? v dd ? v ddq commercial 0c to +70c 3.3v 5% 3.3v / 2.5v 5% industrial -40c to +85c 3.3v 5% 3.3v / 2.5v 5% linear? burst?address? table ? (mode?=? v ss ) ? ? absolute?maximum? ratings (1) ? symbol? parameter ? ? value ? unit t stg storage temperature C65 to +150 c p d power dissipation 1.6 w i out output current (per i/o) 100 ma v in , v out voltage relative to v ss for i/o pins C0.5 to v ddq + 0.3 v v in voltage relative to v ss for C0.3 to 4.6 v for address and control inputs notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may affect reli- ability. 2. this device contains circuity to protect the inputs against damage due to high static voltages or electric felds; however, precau- tions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. this device contains circuitry that will ensure the output devices are in high-z at power up. 0,0 1,0 0,1 a1', a0' = 1,1
integrated silicon solution, inc. www.issi.com 13 rev.? d ? 08/11/2011 ? is61nlf12836a/is61nvf12836a is61nlf25618a/is61nvf25618a? ? power ? supply? characteristics (1) ? (over operating range) ? 6.5? 7.5 ? max? max ? symbol? parameter ? test ?conditions? temp. ? range?? x18? x36 ? ? x18? x36 ? ? uni t ? i cc ac operating device selected, com. 175 175 155 155 ma supply current oe = v ih , zz v il , ind. 180 180 160 160 all inputs 0.2v or v dd C 0.2v, cycle time t kc min. typ. (2) 120 110 i sb standby current device deselected, c om . 90 90 90 90 ma ttl input v dd = max., ind. 100 100 100 100 all inputs v il or v ih , zz v il , f = max. i sbi standby current device deselected, com. 70 70 70 70 ma cmo s input v dd = max., ind. 75 75 75 75 v in v ss + 0.2v or v dd C 0.2v f = 0 typ. (2) 40 40 i sb 2 sleep mode zz > v ih com. 30 30 30 30 ma ind. 35 35 35 35 typ. (2) 20 20 note: 1. mode pin has an internal pullup and should be tied to v dd or v ss . it exhibits 100 a maximum leakage current when tied to v ss + 0.2v or v dd C 0.2v. 2. typical values are measured at v dd = 3.3v, t a = 25 o c and not 100% tested. dc?electrical? characteristics? (over operating range) ? 3.3v? 2.5v ? symbol? parameter ? test ?conditions? min. ? max. ? min. ? max. ? unit ? v oh output high voltage i oh = C4.0 ma (3.3v) 2.4 2.0 v i oh = C1.0 ma (2.5v) v ol output low voltage i ol = 8.0 ma (3.3v) 0.4 0.4 v i ol = 1.0 ma (2.5v) v ih input high voltage 2.0 v dd + 0.3 1.7 v dd + 0.3 v v il input low voltage C0.3 0.8 C0.3 0.7 v i li input leakage current v ss v in v dd (1) C5 5 C5 5 a i lo output leakage current v ss v out v ddq , oe = v ih C5 5 C5 5 a operating ?range?(is61nvfx) ? range ? ambient? temperature ? v dd ? v ddq commercial 0c to +70c 2.5v 5% 2.5v 5% industrial -40c to +85c 2.5v 5% 2.5v 5%
14 integrated silicon solution, inc. www.issi.com rev.? d 08/11/2011 ? is61nlf12836a/is61nvf12836a is61nlf25618a/is61nvf25618a? ? 3.3v?i/o? ac? test?conditions ? parameter ? unit ? input pulse level 0v to 3.0v input rise and fall times 1.5 ns input and output timing 1.5v and reference level output load see figures 1 and 2 317 5 pf including jig and scope 351 output +3.3v figure?1 figure?2 capacitance (1,2) ? symbol? parameter ? conditions? max. ? unit ? c in input capacitance v in = 0v 6 pf c out input/output capacitance v out = 0v 8 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25c , f = 1 mhz, v dd = 3.3v. 3.3v?i/o?output? load? equivalent 1.5v output zo= 50? 50?
integrated silicon solution, inc. www.issi.com 15 rev.? d ? 08/11/2011 ? is61nlf12836a/is61nvf12836a is61nlf25618a/is61nvf25618a? ? 2.5v?i/o? ac? test?conditions ? parameter ? unit ? input pulse level 0v to 2.5v input rise and fall times 1.5 ns input and output timing 1.25v and reference level output load see figures 3 and 4 z o = 50 1.25v 50 output 1,667 5 pf including jig and scope 1,538 output +2.5v figure?3 figure?4 2.5v?i/o?output? load? equivalent
16 integrated silicon solution, inc. www.issi.com rev.? d 08/11/2011 ? is61nlf12836a/is61nvf12836a is61nlf25618a/is61nvf25618a? ? read/write?cycle?switching? characteristics (1) ? (over operating range) ? ? ? ?6.5? ??7.5 ? symbol? parameter ? min. ? max. ? min. ? max. ? unit fmax clock frequency 133 117 mhz t kc cycle time 7.5 8.5 ns t kh clock high time 2.2 2.5 ns t kl clock low time 2.2 2.5 ns t kq clock access time 6.5 7.5 ns t kqx (2) clock high to output invalid 2.5 2.5 ns t kqlz (2,3) clock high to output low-z 2.5 2.5 ns t kqhz (2,3) clock high to output high-z 3.8 4.0 ns t oeq output enable to output valid 3.2 3.4 ns t oelz (2,3) output enable to output low-z 0 0 ns t oehz (2,3) output disable to output high-z 3.5 3.5 ns t as address setup time 1.5 1.5 ns t ws read/write setup time 1.5 1.5 ns t ces chip enable setup time 1.5 1.5 ns t se clock enable setup time 1.5 1.5 ns t ad vs address advance setup time 1.5 1.5 ns t ds data setup time 1.5 1.5 ns t ah address hold time ? 0.5 0.5 ns t he clock enable hold time 0.5 0.5 ns t wh write hold time 0.5 0.5 ns t ceh chip enable hold time 0.5 0.5 ns t ad vh address advance hold time 0.5 0.5 ns t dh data hold time 0.5 0.5 ns t pds zz high to power down 2 2 cyc t pus zz low to power down 2 2 cyc notes: 1. confguration signal mode is static and must not change during normal operation. 2. guaranteed but not 100% tested. this parameter is periodically sampled. 3. tested with load in figure 2.
integrated silicon solution, inc. www.issi.com 17 rev.? d ? 08/11/2011 ? is61nlf12836a/is61nvf12836a is61nlf25618a/is61nvf25618a? ? sleep?mode? timing sleep?mode?electrical? characteristics ? symbol? parameter ? conditions? min. ? max. ? unit ? i sb 2 current during sleep mode zz v ih 35 ma t pds zz active to input ignored 2 cycle t pus zz inactive to input sampled 2 cycle t zzi zz active to sleep current 2 cycle t rzzi zz inactive to exit sleep current 0 ns don't care deselect or read only deselect or read only t rzzi clk zz isupply all inputs (e xcept zz) outputs (q) i sb2 zz setup cycle zz reco ve ry cycle nor mal operation cycle t pds t pus t zzi high-z
18 integrated silicon solution, inc. www.issi.com rev.? d 08/11/2011 ? is61nlf12836a/is61nvf12836a is61nlf25618a/is61nvf25618a? ? read?cycle? timing clk ad v address w rite c ke c e o e data out a1 a2 a3 t kh t kl t kc don't care undefined no tes: write = l means we = l and bwx = l we = l and bwx = l ce = l means ce1 = l, ce2 = h and ce2 = l ce = h means ce1 = h, or ce1 = l and ce2 = h, or ce1 = l and ce2 = l t se t he t as t ah t ws t wh t ces t ceh t advs t advh t kqx q3-3 q3-4 q3-2 q3-1 q2-4 q2-3 q2-2 q2-1 t oehz t kqhz t kq t oeq q1-1 t oehz
integrated silicon solution, inc. www.issi.com 19 rev.? d ? 08/11/2011 ? is61nlf12836a/is61nvf12836a is61nlf25618a/is61nvf25618a? ? write?cycle? timing clk ad v address w rite c ke c e o e data in data out a1 a2 a3 t kh t kl t kc t se t he don't care undefined no tes: write = l means we = l and bwx = l we = l and bwx = l ce = l means ce1 = l, ce2 = h and ce2 = l ce = h means ce1 = h, or ce1 = l and ce2 = h, or ce1 = l and ce2 = l q0-4 t ds t dh d3-3 d3-4 d3-2 d3-1 d2-4 d2-3 d2-2 d2-1 d1-1 t oehz
20 integrated silicon solution, inc. www.issi.com rev.? d 08/11/2011 ? is61nlf12836a/is61nvf12836a is61nlf25618a/is61nvf25618a? ? single?read/write?cycle? timing clk c ke address w rite c e ad v o e data out data in t se t he t kh t kl t kc don't care undefined no tes: write = l means we = l and bwx = l ce = l means ce1 = l, ce2 = h and ce2 = l ce = h means ce1 = h, or ce1 = l and ce2 = h, or ce1 = l and ce2 = l a1 a2 a3 a4 a5 a6 a7 a8 a9 d5 d2 t oelz t oeq q1 q3 q4 q6 q7 t ds t dh
integrated silicon solution, inc. www.issi.com 21 rev.? d ? 08/11/2011 ? is61nlf12836a/is61nvf12836a is61nlf25618a/is61nvf25618a? ? cke ? operation? timing a1 a2 a3 a4 a5 a6 q1 clk cke address write ce ad v oe data out data in d2 t se t he t kh t kl t kc t kqlz t kqhz t kq t dh t ds don't care undefined no tes: write = l means we = l and bwx = l ce = l means ce1 = l, ce2 = h and ce2 = l c e = h means ce1 = h, or ce1 = l and ce2 = h, or ce1 = l and ce2 = l q3 q4 d5
22 integrated silicon solution, inc. www.issi.com rev.? d 08/11/2011 ? is61nlf12836a/is61nvf12836a is61nlf25618a/is61nvf25618a? ? ce? operation? timing don't care undefined clk cke address write ce ad v oe data out data in t se t he t kh t kl t kc no tes: write = l means we = l and bwx = l ce = l means ce1 = l, ce2 = h and ce2 = l ce = h means ce1 = h, or ce1 = l and ce2 = h, or ce1 = l and ce2 = l a1 a2 a3 a4 a5 d5 d3 t dh t ds t oelz t oeq q1 q2 q4 t kqhz t kqlz t kq
integrated silicon solution, inc. www.issi.com 23 rev.? d ? 08/11/2011 ? is61nlf12836a/is61nvf12836a is61nlf25618a/is61nvf25618a? ? ordering? information?(v dd ?=?3.3v/v ddq ?=?2.5v/3.3v) commercial ? range: ?0c?to?+70c ? access? time? order ? part?number? package ? ? 128kx36 6.5 is61nlf12836a-6.5tq 100 tqfp is61nlf12836a-6.5b2 119 pbga is61nlf12836a-6.5b3 165 pbga 7.5 is61nlf12836a-7.5tq 100 tqfp is61nlf12836a-7.5b2 119 pbga is61nlf12836a-7.5b3 165 pbga ? ? 256kx18 6.5 is61nlf25618a-6.5tq 100 tqfp is61nlf25618a-6.5b2 119 pbga is61nlf25618a-6.5b3 165 pbga 7.5 is61nlf25618a-7.5tq 100 tqfp is61nlf25618a-7.5b2 119 pbga is61nlf25618a-7.5b3 165 pbga industrial? range: ?-40c?to?+85c ? access? time? order ? part?number? package ? ? ? 128kx36 6.5 is61nlf12836a-6.5tqi 100 tqfp is61nlf12836a-6.5b2i 119 pbga is61nlf12836a-6.5b3i 165 pbga 7.5 is61nlf12836a-7.5tqi 100 tqfp is61nlf12836a-7.5tqli 100 tqfp, lead-free is61nlf12836a-7.5b2i 119 pbga is61nlf12836a-7.5b3i 165 pbga is61nlf12836a-7.5b3li 165 pbga, lead-free ? ? ? 256kx18 6.5 is61nlf25618a-6.5tqi 100 tqfp is61nlf25618a-6.5b2i 119 pbga is61nlf25618a-6.5b3i 165 pbga 7.5 is61nlf25618a-7.5tqi 100 tqfp is61nlf25618a-7.5tqli 100 tqfp, lead-free is61nlf25618a-7.5b2i 119 pbga is61nlf25618a-7.5b3i 165 pbga
24 integrated silicon solution, inc. www.issi.com rev.? d 08/11/2011 ? is61nlf12836a/is61nvf12836a is61nlf25618a/is61nvf25618a? ? ordering? information?(v dd ?=?2.5v/v ddq ?=?2.5v) commercial ? range: ?0c?to?+70c ? access? time? order ? part?number? package ? ? 128kx36 6.5 is61nvf12836a-6.5tq 100 tqfp is61nvf12836a-6.5b2 119 pbga is61nvf12836a-6.5b3 165 pbga 7.5 is61nvf12836a-7.5tq 100 tqfp is61nvf12836a-7.5b2 119 pbga is61nvf12836a-7.5b3 165 pbga ? ? 256kx18 6.5 is61nvf25618a-6.5tq 100 tqfp is61nvf25618a-6.5b2 119 pbga is61nvf25618a-6.5b3 165 pbga 7.5 is61nvf25618a-7.5tq 100 tqfp is61nvf25618a-7.5b2 119 pbga is61nvf25618a-7.5b3 165 pbga industrial? range: ?-40c?to?+85c ? access? time? order ? part?number? package ? ? 128kx36 6.5 is61nvf12836a-6.5tqi 100 tqfp is61nvf12836a-6.5b2i 119 pbga is61nvf12836a-6.5b3i 165 pbga 7.5 is61nvf12836a-7.5tqi 100 tqfp is61nvf12836a-7.5b2i 119 pbga is61nvf12836a-7.5b3i 165 pbga ? ? 256kx18 6.5 is61nvf25618a-6.5tqi 100 tqfp is61nvf25618a-6.5b2i 119 pbga is61nvf25618a-6.5b3i 165 pbga 7.5 is61nvf25618a-7.5tqi 100 tqfp is61nvf25618a-7.5b2i 119 pbga is61nvf25618a-7.5b3i 165 pbga
integrated silicon solution, inc. www.issi.com 25 rev.? d ? 08/11/2011 ? is61nlf12836a/is61nvf12836a is61nlf25618a/is61nvf25618a? ?
26 integrated silicon solution, inc. www.issi.com rev.? d 08/11/2011 ? is61nlf12836a/is61nvf12836a is61nlf25618a/is61nvf25618a? ?
integrated silicon solution, inc. www.issi.com 27 rev.? d ? 08/11/2011 ? is61nlf12836a/is61nvf12836a is61nlf25618a/is61nvf25618a? ? 1. controlling dimension : mm . note : package outline 08/28/2008

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